Fabless semiconductor company Panmnesia and global hyperscaler Meta have jointly proposed a next generation artificial intelligence datacenter architecture that makes an entire facility behave like a single chip. The work is published as an invited review in Nature Reviews Electrical Engineering, a Nature Portfolio journal. It addresses growing latency and coordination challenges as AI models scale into trillions of parameters.
The Challenge of Scaling Beyond the Rack
As AI models grow into the trillions of parameters, a single training step can require hundreds to thousands of accelerators exchanging terabytes of data. Because progress is determined by the slowest component, latency variability across devices causes frequent delays and unpredictable completion times. Existing connections between racks still depend on general purpose networks such as Ethernet or InfiniBand, where software coordination layers widen the latency spread.
A CXL Based Single Domain Architecture
The proposed design places CPUs, accelerators and memory in a single Compute Express Link based domain and extends cache coherence from within a rack to the entire datacenter. Three hardware elements bound latency variability: a high fan out non blocking switch, a link acceleration unit and a fabric controller. Optical links based on CXL over optics are also outlined to overcome the physical reach limits of electrical signaling.
The Role of Open Standards
CXL is an open industry standard developed collaboratively by semiconductor and infrastructure companies, allowing adoption across the industry without vendor lock in. This open foundation is central to the goal of creating a datacenter that behaves with the predictability of a single chip. By minimizing latency variability beyond the rack, the design targets a larger and more stable unit of execution for AI jobs.
Performance Gains and Operational Benefits
Compared with a conventional rack scale reference platform where one CPU coordinates two accelerators, the new architecture allows a single CPU to coordinate sixteen accelerators. The coherence domain grows to as many as 960 accelerators, roughly thirteen times the reference platform. Round trip latency falls from the microsecond range to several hundred nanoseconds, and a failure replacement unit narrows from an entire server to a single device.
Industry Recognition and Commercial Progress
Nature Reviews Electrical Engineering publishes reviews by invitation only, making the selection of Panmnesia a notable recognition of its CXL expertise. Panmnesia is the first semiconductor startup worldwide to lead such a review, and the article is the first review in the journal to address CXL technology and AI datacenter architecture. The company has implemented the core components of the architecture in silicon, completed validation, and is preparing them for commercial supply.
Executive Viewpoint
Myoungsoo Jung, CEO of Panmnesia, said that connecting large numbers of accelerators and memory devices quickly and efficiently is becoming as important as the performance of individual accelerators. He explained that the research outlines a direction for next generation AI infrastructure in which CXL enables an entire datacenter to operate as a single computing system. This perspective positions CXL as a critical enabler for more stable and scalable AI workloads.
The collaboration between Meta and Panmnesia illustrates how open standard interconnects can reshape AI infrastructure beyond traditional rack boundaries. By reducing latency variability and widening the coherent domain, the proposed architecture supports larger models and more efficient shared infrastructure. As the company moves toward commercial supply, the work offers a practical blueprint for the next generation of AI datacenter design.