The AI-Native Chip Design Challenge, jointly run by European innovation agencies SPRIND and NADI, seeks pioneering teams capable of compressing chip development from years to weeks by making AI an active driver of the chip-design process. The initiative focuses on high-performance, energy-efficient architectures for AI inference and training, including applications connected to European strengths such as data security, biotechnology, robotics, and mobility.
Program Overview
• Organizers: SPRIND and NADI (National Agency for Disruptive Innovation), which is currently being established in the Netherlands.
• Core challenge: Designing high-efficiency AI chips in weeks rather than years using AI-native systems.
• Goal: Use AI to drastically shorten the design process for high-performance chips and develop concrete, production-ready chip designs tailored to AI applications.
• Context: AI is rapidly transforming fields including medicine, mobility, energy, and data security, while semiconductor development remains comparatively slow and costly.
• Opportunity: Emerging AI models and open-source technologies are lowering barriers to chip design and creating new opportunities for European semiconductor innovation.
• Scope: From architecture search and exploration to RTL generation and verification, AI systems are expected to autonomously drive and optimize significant parts of the development workflow through approaches including reinforcement learning and autonomous agents.
• Competition duration: 20 months across two stages, with an independent jury of recognized experts supporting SPRIND and NADI in selecting and evaluating participating teams.
• Support offered: Fixed-price development contracts, access to collaboration partners and experts, technical and commercial support, and potential follow-on funding after Stage 2.
Challenge Pillars
• Pillar 1 – Chip Design: Focuses on developing chip architectures for high-performance AI inference and training. Target areas include processors for AI data centers, AI accelerators such as GPUs and TPUs, application-specific integrated circuits (ASICs), and heterogeneous systems.
• Pillar 2 – AI-Powered Chip Design: Focuses on transforming the chip-design process itself. AI systems should increasingly perform tasks ranging from architecture exploration and optimization to RTL generation and verification, with the aim of reducing development timelines from years to weeks.
Eligible Technologies
• Primary focus: CMOS-based chip architectures.
• Also eligible: Photonic, neuromorphic, memristive, and analog computing concepts.
• Explicitly encouraged: Novel architectural approaches including in-memory computing, heterogeneous integration, and 3D stacking.
• Excluded: Organoid computing platforms and quantum computing chips.
Full-Stack Approach
• The Challenge treats chip design as a system-level problem in which hardware, software, and industrial applications need to work together.
• An end-to-end stack is considered important for real-world deployment.
• Teams are expected to develop the software stack alongside the hardware from the beginning and provide compatibility through optimized Hardware Abstraction Layers (HALs).
• Independent and open platforms are preferred, while solutions that create dependence on a single supplier, such as CUDA-based lock-in, are discouraged.
Ecosystem Role
• Successful chip design depends on close interaction with manufacturing, packaging, EDA tools, material systems, and industrial applications.
• The Challenge aims to involve relevant technology and equipment suppliers, research and innovation centers, and industrial pilot lines from an early stage.
• Industrial end-users may participate as co-designers, launch partners, and validation partners in sectors including data centers, automotive, logistics, and digital infrastructure.
Funding and Support
• Overall program budget: €40 million.
• Maximum support per team: Up to €9.6 million excluding VAT across both stages.
• Stage 1: Seven teams can receive up to €2.6 million each over 8 months.
• Stage 2: Three teams are expected to advance and can receive up to an additional €7.0 million each over 12 months.
• Funding mechanism: Pre-Commercial Procurement (PCP) through individual fixed-price contracts based on each team's estimated costs.
• Eligible costs: Personnel expenses for interdisciplinary teams including chip architects, RTL designers, verification engineers, software developers, and AI/ML specialists; material costs; and eligible operating expenses related to activities such as company formation, patent strategy, and building value-chain partnerships.
• Additional support: Access to potential collaboration partners as well as technical and commercial expertise throughout the Challenge.
• Follow-on funding: After Stage 2, outstanding teams may be targeted for follow-on financing in the tens of millions of euros to support execution of their designs during the tape-out phase. Details will be announced later.
Application Process and Evaluation
• Application deadline: November 30, 2026, at 11:00 GMT+1, equivalent to 10:00 GMT+0. Applications submitted by the deadline will be considered.
• Detailed application requirements are provided in the official call for submissions and participation agreement.
• Evaluation: Submissions are assessed against the criteria established in the official Challenge documentation.
• Shortlisting: Selected teams will be invited to present their proposals to an independent jury of experts.
• Final selection: The jury will determine which teams advance into the Challenge following the pitch process.
Timeline
• September 23, 2026: Challenge launch and application period opens.
• November 30, 2026, 11:00 GMT+1 / 10:00 GMT+0: Application deadline.
• December 14–15, 2026: In-person jury pitches in Leipzig.
• December 16, 2026: Challenge activities are scheduled to begin for selected teams.
Webinar Schedule
• October 9, 2026, from 4:00 PM to 5:30 PM CEST, equivalent to 3:00 PM to 4:30 PM GMT+1.
• November 17, 2026, from 4:00 PM to 5:30 PM CET, equivalent to 4:00 PM to 5:30 PM GMT+1.
• Further details are expected to be announced through SPRIND's communication channels.
Who Can Apply
• Eligible applicants: Individual companies working on chip design, as well as teams or consortia of up to three companies with complementary core competencies, represented by a single lead contact.
• Pure research groups and individual research institutions are generally not eligible as standalone applicants. The Challenge is designed around commercial implementation and the development of sustainable businesses.
• Commercial focus: Participating teams are expected to translate the intellectual property created through the Challenge into viable commercial applications and long-term business activity.
• Geographic requirement: Applicant companies must be headquartered in the European Union, European Free Trade Association (EFTA), or United Kingdom. Individual team members and collaboration partners may be located outside these regions.
IP Regulations
• SPRIND uses the European Pre-Commercial Procurement (PCP) framework to implement the Challenge.
• PCP enables public authorities to procure research and development services through structured development contracts rather than conventional equity investment.
• Intellectual-property terms are governed by the official participation agreement and applicable European procurement and state-aid requirements.
• Applicants should review the IP provisions in the official Challenge documentation carefully before applying.
With an overall budget of €40 million, up to €9.6 million in support per participating team across both stages, and links to industrial partners, technical experts, and potential follow-on financing, the AI-Native Chip Design Challenge targets commercially oriented teams seeking to rethink both AI-chip architectures and the way chips themselves are designed. Applications remain open until November 30, 2026, at 11:00 GMT+1, equivalent to 10:00 GMT+0.